1. Field of Invention
The present invention relates to a static random access memory (SRAM) structure. More particularly, the present invention relates to an SRAM having a common bit line structure.
2. Description of Related Art
As the functions of a microprocessor become more powerful, the size of software programs capable of being executed by a computer increases. In line with this trend, the need for high capacity memories increases. Therefore, how to produce high-density memories at a moderate cost is still a major issue in the semiconductor industry.
According to the difference in read/write function, a memory can be classified into two types, namely, read only memory (ROM) and random access memory (RAM). ROM is a kind of memory that allows reading from the memory only while RAM can perform both read and write functions. According to the method of data storage, ROM can be further divided into a mask ROM, a programmable ROM (PROM), an erasable programmable ROM (EPROM) and electrically erasable programmable ROM (EEPROM). According to the method of data processing within the memory, random access memory can be further classified into a static RAM (SRAM) and dynamic RAM (DRAM).
In digital data storage, a bit is generally regarded as a basic unit, and a memory cell is the device for storing a bit within the memory. FIG. 1 is an equivalent circuit diagram showing two memory cells and its associated circuit structure of a conventional SRAM. Since the structure of memory cell 10 and its associated circuits are very similar to that of memory cell 20, memory cell 10 and its associated circuits can be used as an example to explain the workings of an SRAM.
The memory cell 10 comprises four N-channel metal-oxide-semiconductor (NMOS) transistors and two resistors, wherein transistors T11 and transistor T12 are pull-down transistors, transistor T13 and transistor T14 are pass transistors, and resistors R11 and R12 are load resistors. The drain of the pass transistor T13 is connected to one end of the pull down transistor T11, and the drain of the pass transistor T14 is connected to one end of the pull down transistor T12. The gate of the pass transistor T13 and the gate of the pass transistor T14 are connected to a word line (WL) which can be used to access data within the memory cell 10. In general, each memory cell is connected to two bit lines.
For example, the source of the pass transistor T13 is coupled to a bit line BL1 while the source of the pass transistor T14 is coupled to a complementary bit line BLB1.
An Y-pass transistor T31 of the bit line BL1 and an Y-pass transistor T34 of the complementary bit line BLB1 are controlled by an Y-select signal YS1. Similarly, a Y-pass transistor T32 of the bit line BL1 and a Y-pass transistor T33 of the complementary bit line BLB1 are controlled by another Y-select signal YSB 1.
From the above description and equivalent circuit diagram shown in FIG. 1, it is obvious that each SRAM comprises a bit line and a complementary bit line. As the level of integration for SRAM increases, not only is the method of arrangement and the size of each memory cell becomes important, the number of metal lines running into the array of cells is critical too. Hence, if metal lines running into the memory cell array can be reduced, product yield and memory capacity of the memory can be improved as well.
In light of the foregoing, there is a drive for reducing the number of metal lines demanded by a memory cell array.